To the extent that in a track mode it acquires a value of an input analog signal and in a hold mode it stores it for a length of time, a track and hold amplifier may be thought of as a dynamic analog memory. The "slew rate" is the term given to the speed with which it acquires and the "acquisition time" is the term given to the time which it takes to acquire the value of the voltage of the impressed analog signal in the track mode. The "droop rate" is the term given to the temporal stability of the acquired value of the voltage in the hold mode. The greater the slew rate and bandwidth and the lesser the acquisition time, droop rate and power, the better a fast track and hold amplifier is able to cyclically perform its signal tracking and holding functions.
Among others, track and hold amplifiers find application in analog-to-digital (A/D) converters. For this application, the track and hold amplifier samples an input analog signal and stores its value long enough to allow for the analog-to-digital (A/D) conversion thereof. By way of example, Micro Networks, the instant assignee, provides a fast track and hold amplifier identified as the "Micro Networks MNHT1010" Track and Hold, believed to presently be the fastest commercially-available device, that exhibits a slew rate of 1000 V/.mu.Sec, a small signal bandwidth of 200 MHz, an acquisition time of 10 nSec to 0.1%, a droop rate of 500 mV/mSec and a power dissipation of 2.3 W.
The heretofore known fast track and hold amplifiers employ an open-loop architecture in which the input signal to be tracked and held is impressed through an input buffer to one signal node of a diode switching bridge. A hold capacitor is connected to the other signal node of the diode switching bridge. The output signal is available at the output of a unitary-gain FET buffer the input of which is connected to the hold capacitor. Fixed current sources are connected to the feed nodes of the diode switching bridge. The input buffer isolates the impressed analog input signal from bridge transients produced by bridge switching, and the output buffer presents both a high input impedance and a low output impedance to enable optimum coupling to downstream electronic subsystems, such as an A/D conversion subsystem.
In the track mode, the diodes of the diode switching bridge are forward-biased, so that the fixed current sources are electrically connected to the hold capacitor. The voltage across the hold capacitance is thereby constrained to be the same as the impressed input analog voltage, and the fixed current sources supply the charge that enables the same to charge up to the value of the voltage of the impressed analog signal.
In the hold mode, the diodes of the diode switching bridge are reverse-biased, so that on the one hand the fixed current sources are electrically disconnected from the hold capacitor and on the other the hold capacitor is electrically disconnected from the input buffer. With the input to the hold capacitor in the open-circuit condition, the hold capacitor is thereby enabled to hold the corresponding sampled value of the voltage of the impressed analog signal.
The slew rate of the heretofore known open-loop track and hold amplifiers has been fixed by the particular ratio of the magnitude of the current selected for the fixed current sources that supply charge to the hold capacitor to the value of the capacitance selected for the hold capacitor. On the one hand, the higher the value of the magnitude of the current the faster the slew rate that the heretofore known open-loop track and hold amplifiers exhibit. However, the current magnitude, and corresponding slew rate, are fundamentally limited by the power handling capability of the constitutive diodes and switching transistors of the diode switching bridge of the heretofore known open-loop fast track and hold amplifiers. Beyond an upper current bound, these devices generate more heat they are able to dissipate, which places an upper bound on the slew rate for a given value of capacitance. On the other hand, the smaller the value of the hold capacitance the faster is the corresponding slew rate and the larger is the corresponding droop rate of the heretofore known open-loop fast track and hold amplifiers. However, in a practicable embodiment, a range is imposed on the possible values that can be selected for the capacitance of the hold capacitors of the heretofore known open-loop track and hold amplifiers. The maximum boundary for the range of hold capacitance is determined by the selection criteria that it must be big enough to handle the magnitude of the current selected to provide an acceptable slew rate, and the minimum boundary of the range of track and hold capacitance is determined by the selection criteria that it must not be so small as to fail to provide an acceptable droop rate.
The bandwidth of the heretofore open-loop fast track and hold amplifiers has been limited by the nature of the analog signal path that is seen by the impressed analog signal. The output resistance of the input buffer is in series with the resistance of the diode bridge. This combined resistance forms an RC filter with the hold capacitor. In addition to these nominal resistances an added isolation resistor is sometimes necessary between the input buffer and the diode switching bridge to provide critical dampening for best acquisition time. The values of the resistances and of the hold capacitor produce a pole in the analog signal path that places an upper bound on the bandwidth of the heretofore known open-loop architectures that heretofore has been impossible to get around.
In the hold mode, the droop rate limitation of the heretofore known open-loop fast track and hold amplifiers has been imposed by the way that the voltage on the hold capacitor is undesirably discharged both by gate current drawn by the FET input stage of the unitary-gain FET output buffer and by reverse leakage currents of mismatched diodes of the diode switching bridge. For the comparatively high currents required to achieve acceptable slew rates, the temperatures of the heretofore known fast track and hold amplifiers increase towards their maximum power dissipating bound. But as the temperature increases, the gate currents of the FET input stage exponentially increase, producing correspondingly larger droop rates.